1. Field of the Invention
The present invention relates to a cross-connection switch for use in a cross-connection device capable of switching a destination for each channel in a network including a circuit in which a plurality of channels are multiplexed in the transmission of a digital signal.
2. Description of the Related Art
Recently, data transmitted through a transmission line are not only voice data but also multimedia information such as an image data, etc., thereby requiring a high-speed and large-capacity network. In this case, it is desired to have an exchange or a cross-connection device capable of accommodating the largest possible number of lines to perform a high-speed switching process.
FIG. 1 shows the configuration of a switch unit (cross-connection switch) for switching in time and space a frame signal in channel units in the conventional cross-connection device.
In FIG. 1, the cross-connection switch receives data (frames) through input lines 1 through 4, cross-connects the data (switching the data to respective destinations in channel units), and outputs the cross-connected data (frames) to the input lines 1 through 4. In this example, the cross-connection switch is provided with unit switches 149-1 through 149-4 for the corresponding output lines. Each of the switches receives signals (frames) of the input lines 1 through 4, cross-connects the input signals (input frames), and outputs the cross-connected signals (output frames) to the input lines 1 through 4. Since the unit switches 149-2 through 149-4 have the same configuration as the unit switch 149-1, their internal configurations are omitted here. Also in FIG. 1, the number of accommodated lines is 4, but the configuration of the cross-connection switch is not limited to this configuration, and can be modified depending on the number of cross-connected lines.
A serial signal input through the input lines 1 through 4 is converted into a parallel signal of n bits (n is a positive integer) by serial-parallel converters 155 through 158. The serial-parallel conversion is performed for each channel of an input signal (input data) in one frame. In the serial-parallel converters 155 through 158, an input signal converted into a parallel signal is stored in memory 150 through 153. Parallel signals are stored in channel units. That is, a parallel signal of each channel is stored at one address.
An address read control unit 154 provides a read address 170 of a parallel signal for the memory 150 through 153 at an instruction from the control unit (not shown in the figure) of a cross-connection device. When the read address 170 is input, the parallel signal on each channel output from the memory 150 through 153 is input to a 4-1 selector 159. The address read control unit 154 applies a selection signal SEL to the 4-1 selector 159 such that a parallel signal output from any of the memory 150 through 153 can be switched and output for each channel. Thus, the parallel signal on each channel of each frame input from the input lines 1 through 4 is exchanged in time and space, and output to a parallel-serial converter 160. The parallel signal on each channel is converted into a serial signal by the parallel-serial converter 160 for each channel, synchronized with each time slot of an output frame, and output to an output line 1.
Similarly, each of the other unit switches 149-2 through 149-4 outputs an output frame to output lines 2 through 4.
As described above, the conventional cross-connect device performs a cross-connecting process after converting a signal on one channel assigned to a time slot of each frame input in series into a parallel signal.
That is, in the conventional configuration shown in FIG. 1, a frame of multiplexed signal on one channel is designed in n-bit units (n is a positive integer), and is switched in time division manner in n-bit units.
Since a signal in the input lines 1 through 4 is serial-parallel converted, there arises an n clock+0.5 clock delay (for a process in the opposition phase to keep a margin) until n-bit parallel data (data on one channel) is prepared before starting the switching process. One clock in this process refers to a clock synchronous with a 1-bit signal in an input frame. That is, to make a signal transmitted in series through the input lines 1 through 4 into an n-bit parallel signal, it is necessary to input the n-bit signal to the serial-parallel converters 155 through 158, thereby generating an n-clock delay. In addition, to correctly latch the value of a serial signal, the serial-parallel converters 155 through 158 should latch it in the middle of a 1-bit signal. To attain this, the serial-parallel converters 155 through 158 perform a process in the opposition phase of the clock to keep a margin. Therefore, each bit of signal is latched according to a phase-adjusted clock with the phase of the clock shifted by 0.5 clock from the input signal. As a result, a further 0.5-clock delay is generated.
Since the parallel-serial conversion is performed after the switching process and the result is output through the line, the 0.5 clock delay arises again (to perform the process in the in-phase to reserve a margin for the data processed in the opposition phase as described above). Accordingly, a delay time of at least (n clock+1 clock) arises before the line signal input to the unit switches 149-1 through 149-4 is output to the output lines 1 through 4.
In addition, with the configuration shown in FIG. 1, the switching process is performed after converting the serial data (serial signal) into parallel data (parallel signal). Therefore, the number of physical memory units and the number of selectors and other necessary lines for switching signals are required corresponding to the accumulated number of bits or lines depending on the number of bits written to the memory (number of bits on one channel) and the number of lines to be simultaneously cross-connected. As a result, the hardware functioning as a cross-connection switch is considerably large.
As described above, with the configuration of the conventional cross-connection switch, a serial signal is first converted into a parallel signal, and then a switching process is performed. Therefore, there has been the problem that a signal transmission delay arises depending on the number of bit on channels to perform the processes by the serial-parallel converter and a parallel-serial converter.
Furthermore, since a serial signal is converted into a parallel signal in the conventional technology, the number of physical memory units and the number of circuits such as selectors for switching a parallel signal become large, thereby resulting in a large hardware. Accordingly, with a larger storage capacity for communications of these days, it is a problem to realize a small cross-connection device with a large capacity.